Abstract
The adopted laser pulse widths in different pulsed time-of-flight (ToF) light detection and ranging (LiDAR) systems from short- to long-distance applications would vary from 1 to ≥100 ns, which demands the timing discrimination (TD) circuit has good adaptability to the input pulsewidth. Meanwhile, the dynamic range (DR) and input common-mode range (ICMR) of the TD circuit are preferred to be as large as possible to reduce the complexity of the front-end circuits. In this article, a TD application-specific integrated circuit (ASIC) is proposed to address the above issues. Featuring rail-to-rail DR and ICMR, the proposed TD circuit consists of a high-speed arming comparator (A-COMP), a low walk error zero-crossing comparator (ZC-COMP), and a robust latch/reset circuit. The rail-to-rail A-COMP has been modified to have low propagation delay and low delay dispersion to improve the accuracy. A novel low walk error input stage with rail-to-rail DR and ICMR is proposed for the ZC-COMP, and resistive-feedback (RFB) inverters combined with a common-mode feedback (CMFB) loop are proposed for reducing the walk error induced by the differential-to-CMOS level conversion. Fabricated in a 0.18- μ m CMOS process and demonstrated as a constant-fraction discriminator (CFD), the ASIC achieves walk errors of ±310, ±130, ±105, and ±50 ps for the input pulses with full-width at half-maximum (FWHM) of 150, 25, 3, and 1 ns, respectively, across a wide DR of 20 mVpp to rail-to-rail amplitude. Comparisons with discrete counterparts and prior works highlight the ASIC’s superior performance in terms of ICMR, DR, walk error, and adaptability to different laser pulse widths.